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商品編號:
EIC0042
商品名稱:
Dolphin SMASH v5.8.3
語系版本:
英文正式版
商品類型:
能完全符合混合模擬與邏輯訊號電路的需求軟體
運行平台:
WIN9x/WINME/WINNT/WIN2000/WINXP/WIN2003
更新日期:
2007-06-18
碟片數量:
1片
銷售價格:
100
瀏覽次數:
19581
熱門標籤:

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Dolphin SMASH v5.8.3
Dolphin SMASH v5.8.3 英文正式版(能完全符合混合模擬與邏輯訊號電路的需求軟體)


破解說明:
破解檔放置於crack夾內,請將破解檔複製於主程式的安裝目錄內既可破解
內容說明:
混合信號兼顧多層次模擬軟體,能完全符合混合模擬與邏輯訊號電路的需求。混合訊號
指的是SMASH能處理模擬或是連續時間的訊號與不連續時間的訊號,例如:邏輯(二進位
binary)或數字(十進位 decimal)。 多層次指的是SMASH並沒有被限制在某些modeling
level上,即SMASH能處理晶體管層次、閘階層次、功能層次、行為層次並與來自於模擬
與邏輯的子電路加以混合模擬。 意味著SMASH可用在任何層次上的設計作一些精確的電
路修正,這表示你將能輕易處理任何複雜性的電路。另外SMASH有強大的多語言功能,
能與SPICE、Verilog-HDL、 VHDL、ABCD(C-language)與VHDL-AMS相容,可以將模擬區
塊以SPICE語法描述與數字區塊以Verilog-HDL語法或 VHDL語法描述的設計作多層次混
合信號模擬。SMASH能快速地模擬驗證所設計的混合信號晶片,非常適合用來解決混合
信號晶片設計問題,以提供高效能的混合信號晶片設計模擬驗證環境,減化複雜電路模
擬驗證的程式,縮短晶片設計的時程。
英文說明:
SMASH 5.8 extends its capabilities for mixed signal
code-coverage and sensitivity-analysis up to detecting flaws
in Virtual Testbenches and to identifying circuit weaknesses
for the DfM conscious designer. Improvement on the
block-busting GUI features facilitate further the
adjustments of speed versus accuracy, as well as tracing,
now augmented for a hierarchical view applicable to mixed
signal design.

With analysis of sensitivity to dispersion, SMASH provides a
fast and accurate solution for the problems of design for
yield, manufacturability and robust design of
nano-electronic analog circuits. Compared to Monte Carlo
analysis, the sensitivity to dispersion is thousands of
times faster. Furthermore, the sensitivity to dispersion
analysis provides the contribution of each component to the
total dispersion, thus design debugging becomes trivial.

As SCROOGE enables power consumption analysis before Place &
Route, the SPEF back-annotation now provides it with
parasitic capacitance back-annotation for an accurate power
consumption analysis after Place & Route. Parasitic
capacitances are taken into account to back-annotate the
Liberty wire load model. This allows to consider the exact
routing capacitance both for cell interconnection wires and
for clock trees, which represent an important part of the
consumed power.

For increased interoperability, simulation results can now
be exported into standard VCD (Verilog Change Dump) format
for logic or CSDF (Common Simulation Data Format) for reuse
in all compatible EDA solutions. Of course, SMASH can also
import and display VCD or CSDF results as well as.
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